In semiconductor memory, proper operation of the memory is based on the correct timing of various internal command and clock signals. For example, in reading data from the memory, internal clock signals that clock data path circuitry to provide (e.g. output) the read data may need to be provided substantially concurrently with internal read command signals to properly enable the data path circuitry to output the read data. If the timing of the internal read command signal is not such that the data path circuitry is enabled at the time the internal clock signal clocks the data path circuitry to output the read data at an expected time, the read command may be inadvertently ignored or the read data provided by the memory may not be correct (e.g., the data associated with another read command). Likewise, in writing data to memory internal clock signals that clock data path circuitry to latch write data may need to be provided with specific timing relationships with internal write command signals to properly enable the data path circuitry to provide the latched write data for writing to memory. Inaccurate timing of the internal command and clock signals could result in the write command being inadvertently ignored or incorrect write data being provided to the memory may (e.g., the write data is associated with another write command). Another example of a command that may require the correct timing of internal clock signals and the command for proper operation include, for example, on-die termination enable commands.
Moreover, as known, a “latency” may be selected (e.g., programmed, desired, used, given, etc.) to set a time, typically in numbers of clock periods tCK, between receipt of a read command by the memory and when the data is output by the memory. A “write latency” may also be selected to set a time, also typically in numbers of tCK, between receipt of a write command by the memory and when the write data is provided to the memory. The latencies may be selected, for example, to accommodate clock signals of different frequencies (i.e., different clock periods).
Complicating the generating of correctly timed internal clock and command signals is the relatively high frequency of memory clock signals. For example, memory clock signals can exceed 1 GHz. Further complicating the matter is that multi-data rate memories may provide and receive data at a rate higher than the memory clock signal, which may represent the rate at which commands may be executed. As a result, the timing domains of command and clock signals may need to be crossed in order to maintain proper timing. An example of a multi-data rate memory is one that outputs read data at a rate twice that of the clock frequency, such as outputting data synchronized with clock edges of the memory clock signal. Further complicating the timing of internal clock and command signals with relatively high frequency clock signals is minimum forward path delay through a signal path. That is, in some instances, the minimum forward path delay of a signal path may prevent internal command signals from being provided for operation according to a selected latency.
An example conventional approach of timing internal command and clock signals is modeling both the clock path and the command path to have the same propagation delay. This may require, however, that delays and/or counter circuitry run continuously. As a result, power consumption may be higher than desirable. Additionally, the propagation delay of the various internal clock and command paths can often vary due to power, voltage, and temperature conditions. For clock and command paths having relatively long propagation delay or additional delay circuitry, the variations due to operating conditions may negatively affect the timing of the internal signals to such a degree that the memory does not operate properly.